#ifndef HAL_H
#define HAL_H

#include "xparameters.h"


#include "copro_final.h"

// Offsets' Definition
#define OFFSET_STATUS				0x30
#define OFFSET_CMD					0x2c
#define OFFSET_IRQ					0x28
#define OFFSET_SCAN_PERIOD			0x24
#define OFFSET_MON_LEN				0x20
#define OFFSET_GW_CONFIG			0x1c
#define OFFSET_CONFIG_BUFFER_1		0x18
#define OFFSET_CONFIG_BUFFER_2		0x14
#define OFFSET_CONFIG_BUFFER_3		0x10
#define OFFSET_RESULT_BUFFER_1		0xc
#define OFFSET_RESULT_BUFFER_2		0x8 
#define OFFSET_RESULT_BUFFER_3		0x4
#define OFFSET_RESULT_BUFFER_4		0x0

// Commands' Definition
#define CMD_NOP			0x000000001
#define CMD_START		0x000000002
#define CMD_STOP		0x000000003
#define CMD_RESET		0x000000004
#define CMD_MON_LEN		0x000000005

void write_reg( unsigned int offset, unsigned int value) {	
	COPRO_FINAL_mWriteReg(XPAR_COPRO_FINAL_0_BASEADDR, offset, value);
}

unsigned int read_reg( unsigned int offset ) {
	return COPRO_FINAL_mReadReg(XPAR_COPRO_FINAL_0_BASEADDR, offset);
}

void enable_interrupt()
{
	COPRO_FINAL_EnableInterrupt((void*)XPAR_COPRO_FINAL_0_BASEADDR);
}

void setInterrupt()
{
  /* Mise en place des interruptions */
/*
  copro_final_IRQ_init();
  XExc_Init();
  
  XExc_RegisterHandler(XEXC_ID_NON_CRITICAL_INT,
                       (XExceptionHandler)XIntc_DeviceInterruptHandler,
                       (void *)XPAR_OPB_INTC_0_DEVICE_ID);

  XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,
                        XPAR_OPB_INTC_0_XPS_DDP_RIO_0_IP2INTC_IRPT_INTR,
                        (XInterruptHandler)xps_ddp_rio_IRQ_handler,
                        (void *)0);

  XIntc_mEnableIntr(XPAR_XPS_INTC_0_BASEADDR,
		    XPAR_XPS_DDP_RIO_0_IP2INTC_IRPT_MASK);

  XIntc_mMasterEnable(XPAR_XPS_INTC_0_BASEADDR);
  XExc_mEnableExceptions(XEXC_NON_CRITICAL);

  xps_ddp_rio_IRQ_init();*/
}

#endif // HAL_H